A unit cell of an SRAM device typically consists of two inverters interconnected to operate as a flip-flop. Such unit cells are typically classified as high resistance load type NMOS (N-channel Metal Oxide Semiconductor) memory cells or Complementary Metal Oxide Semiconductor (CMOS) type memory cells. As will be understood by those skilled in the art, NMOS type SRAM devices typically employ a high resistance polysilicon line as a high resistance load element.
FIG. 1 illustrates a unit cell of an SRAM device according to the prior art. Typical SRAM devices are also disclosed in U.S. Pat. No. 4,916,668, entitled "Internal Synchronization Type MOS SRAM with Address Transition Detecting Circuit" and in an article entitled "65A 17ns 64K CMOS RAM with a Schmitt Trigger Sense Amplifier", International Solid-State Circuits Conference Digest of Technical Papers, p. 64, (1985). Referring now to FIG. 1, a conventional four transistor SRAM unit cell comprises a pair of high resistance polysilicon load elements 106 and 107, a pair of cross-coupled NMOS drive transistors 104 and 105, and a pair of NMOS transfer transistors 102 and 103.
The high resistance polysilicon load elements 106 and 107 have first ends connected to a supply line 100 (which is typically coupled to a supply (e.g., VCC) in a peripheral circuit region of an integrated circuit substrate) and second ends connected to the drains of respective NMOS drive transistors 104 and 105 at a pair of nodes N1 and N2. The sources of the drive transistors 104 and 105 are connected to a ground voltage line 101. As will be understood by those skilled in the art, the nodes N1 and N2 store complementary data. This complementary data can be accessed by turning on the NMOS transfer transistors 102 and 103 so that the data on node N1 can be transferred to a bit line B/L and the complementary data on node N2 can be transferred to a complementary bit line B/L.
FIG. 2 illustrates schematically a layout of a memory cell array region 200 and a peripheral circuit region 300 of a semiconductor memory device according to conventional technology. FIG. 3 is a cross sectional view of the layout schematic of FIG. 2, taken along line 3-3'. Referring now to FIGS. 1-3, the supply line 100 is extended from the memory cell array region 200 to the peripheral circuit region 300 and is connected with first ends of the high resistance polysilicon load elements 106 and 107. As illustrated, a metal supply line 108 in the peripheral circuit region 300 is electrically connected to the supply line 100 by means of a contact via 109. This contact via 109 extends partially through a first electrically insulating layer 111 which extends opposite a substrate 400.
Here, the supply line 100 is formed from the same layer of polysilicon as the high resistance polysilicon load elements 106 and 107, but is formed to have a substantially higher electrical conductivity in order to keep the standby current of the memory cell low, increase the stability of the memory cell, and maintain the current supplied to the memory cell through the supply line 100 stable to enhance the memory cell's data storage capacity. In particular, the supply line 100 is preferably doped with an impurity of first conductivity type (e.g. N-type) at a high level while the load elements 106 and 107 are doped with the same impurity but at a much lower level, or with an impurity of second conductivity type (to compensate for the dopant of first conductivity type). Thus, the resistance of the load elements 106 and 107 can be set to a higher level than the resistance of the supply line 100. However, the ability to form load elements 106 and 107 having sufficiently high resistances can be limited as the degree of integration increases because the length of the wiring interconnects and the length of the load elements 106 and 107 decreases.
To address this problem, the thicknesses of the polysilicon load elements 106 and 107 are reduced to maintain the resistances at sufficiently high levels. Similarly, the thickness of the supply line 100 is also typically reduced since it is typically formed by patterning the same layer of polysilicon used to form the load elements 106 and 107. However, as will be understood by those skilled in the art, the use of supply lines 100 which are too thin can lead to reduced reliability and reduced yield in the event such thin lines are accidently overetched during subsequent process steps to form contact vias. For example, as best illustrated by FIG. 4, the polysilicon supply line 100 may be accidently overetched during the step of forming a contact via 109, thereby exposing a lower conductive layer 112. When this occurs, subsequent metal lines including the metal supply line 108 may be formed with poor electrical contact to the polysilicon supply line 100 and with accidental contact (i.e., "short circuit")to a lower conductive layer 112. This reduces device reliability.
One attempt to reduce the likelihood of overetching of thin supply lines is illustrated by FIGS. 5-6. FIG. 5 is an alternative layout schematic view of an electrical interconnect between a polysilicon supply line 100 and a metal supply line 108 and FIG. 6 is a cross-sectional view of the electrical interconnect of FIG. 5, taken along line 6-6'. A conductive layer 121 is used as an intermediate electrical interconnect between a polysilicon supply line 100 which extends from a memory circuit region 200 and a metal supply line 108 which extends from a peripheral circuit region 300. As illustrated, a first contact hole 113 is formed in a first electrically insulating layer 111 prior to formation of the polysilicon supply line 100 and then a second contact hole 109 is formed through a second electrically insulating layer 114 prior to formation of the metal supply line 108. Accordingly, the metal supply line 108 is indirectly electrically connected to the polysilicon supply line 100 by the conductive layer 121. Thus, it is unnecessary to perform an etching step to expose and possibly overetch the polysilicon supply line 100. But, it is necessary to employ an additional conductive layer 121 which means the fabrication steps needed to form the memory device interconnects of FIGS. 5-6 is complicated.
Thus, notwithstanding the above attempts to form integrated circuit memory devices, there continues to be a need for methods of forming integrated circuit memory devices having improved supply line connections.